Low-C ESD protection design with dual resistor-triggered SCRs in CMOS technology

Chun Yu Lin*, Chun Yu Chen

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

2 引文 斯高帕斯(Scopus)

摘要

The electrostatic discharge (ESD) protection design with low parasitic capacitance seen at I/O pad is needed for high-frequency applications. Conventional ESD protection designs with dual diodes or dual stacked diodes have been used for gigahertz applications. To further reduce the parasitic capacitance, the ESD protection design by using complementary resistor-triggered silicon-controlled rectifiers (RTSCRs) is proposed in this paper. The proposed design includes a P-type RTSCR between I/O and VDD, an N-type RTSCR between I/O and VSS, and a power clamp circuit between VDD and VSS to achieve whole-chip ESD protection. Verified in silicon chip, the RTSCRs have the advantages, such as the sufficient low clamping voltage and lower parasitic capacitance, as compared with the conventional ESD protection designs. Therefore, the proposed design is suitable for low-C ESD protection in CMOS technology.

原文英語
頁(從 - 到)197-204
頁數8
期刊IEEE Transactions on Device and Materials Reliability
18
發行號2
DOIs
出版狀態已發佈 - 2018 六月 1

ASJC Scopus subject areas

  • 電子、光磁材料
  • 安全、風險、可靠性和品質
  • 電氣與電子工程

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