Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

Ming Dou Ker*, Chun Yu Lin, Tang Long Chang

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

7 引文 斯高帕斯(Scopus)

摘要

Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.

原文英語
主出版物標題Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
頁面374-377
頁數4
DOIs
出版狀態已發佈 - 2011
對外發佈
事件2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, 臺灣
持續時間: 2011 4月 252011 4月 28

出版系列

名字Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

其他

其他2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
國家/地區臺灣
城市Hsinchu
期間2011/04/252011/04/28

ASJC Scopus subject areas

  • 硬體和架構
  • 電氣與電子工程

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