Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

Ming Dou Ker, Chun-Yu Lin, Tang Long Chang

研究成果: 書貢獻/報告類型會議貢獻

5 引文 斯高帕斯(Scopus)

摘要

Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.

原文英語
主出版物標題Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
頁面374-377
頁數4
DOIs
出版狀態已發佈 - 2011 六月 28
事件2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, 臺灣
持續時間: 2011 四月 252011 四月 28

其他

其他2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
國家臺灣
城市Hsinchu
期間11/4/2511/4/28

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • 引用此

    Ker, M. D., Lin, C-Y., & Chang, T. L. (2011). Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process. 於 Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (頁 374-377). [5783551] https://doi.org/10.1109/VDAT.2011.5783551