Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.
|主出版物標題||Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011|
|出版狀態||已發佈 - 2011 六月 28|
|事件||2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, 臺灣|
持續時間: 2011 四月 25 → 2011 四月 28
|其他||2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011|
|期間||2011/04/25 → 2011/04/28|
ASJC Scopus subject areas