Investigation of Double-Snapback Characteristic in Resistor-Triggered SCRs Stacking Structure

Shiang Shiou Yen, Chun Hu Cheng, Chia Chi Fan, Yu Chien Chiu, Hsiao Hsuan Hsu, Yu Pin Lan, Chun Yen Chang

研究成果: 雜誌貢獻期刊論文同行評審

9 引文 斯高帕斯(Scopus)

摘要

Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current-voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a 0.11μ m 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.

原文英語
文章編號8010910
頁(從 - 到)4200-4205
頁數6
期刊IEEE Transactions on Electron Devices
64
發行號10
DOIs
出版狀態已發佈 - 2017 十月 1

ASJC Scopus subject areas

  • 電子、光磁材料
  • 電氣與電子工程

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