Investigation of consequent process-induced stress for N-type metal oxide semiconductor field effect transistor with a sunken shallow trench isolation pattern

Chang Chun Lee, Chuan Hsi Liu, Rong Hao Deng, Hung Wen Hsu, Kuo Ning Chiang

研究成果: 雜誌貢獻文章

2 引文 斯高帕斯(Scopus)

摘要

The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22 nm and lower. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility.

原文英語
頁(從 - 到)323-328
頁數6
期刊Thin Solid Films
557
DOIs
出版狀態已發佈 - 2014 四月 30

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Surfaces and Interfaces
  • Surfaces, Coatings and Films
  • Metals and Alloys
  • Materials Chemistry

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