Interaction influence of S/D GeSi lattice mismatch and stress gradient of CESL on nano-scaled strained nMOSFETs

Chang Chun Lee*, Yen Ting Kuo, Chuan Hsi Liu


研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)


The intrinsic stress of thin films has become an important resource as advanced strain engineering is introduced into nanoscaled semiconductor devices. The performance of preferred device infrastructure can be studied by estimating stress-induced mobility gain. However, traditional simulation approaches for device stress typically do not consider the eventual consequence of the stress gradient of strained thin films on nanoscaled transistor stress prediction. Thus, the actual operating characteristic of concerned devices can be easily misunderstood. To resolve this issue, this research presents a fabrication-oriented simulation methodology for device stress and combines it with a multi-layered deposition model for thin film. This study aims to explore stress-induced effects on the performance of a Ge-based testing vehicle for 20 nm n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) with Ge1−xSix alloys embedded into the source/drain regions of the device. Intrinsic stress is introduced via a 1.0 GPa tensile contact etch stop layer (CESL). Analysis results indicate that stress contours adjacent to the top of the device gate are different from those obtained using the conventional simulation method. Moreover, greater CESL stress passes through the spacer and reaches the device channel. Furthermore, a relationship between the stress components and piezoresistivity coefficients of the Ge material is adopted to estimate the width dependence of the Ge-based nMOSFET on its mobility gain. A maximum mobility gain of up to 60.87% is acquired from the estimated results, and a channel width of 200 nm is preserved.

頁(從 - 到)254-259
期刊Materials Science in Semiconductor Processing
出版狀態已發佈 - 2017 11月 1

ASJC Scopus subject areas

  • 材料科學(全部)
  • 凝聚態物理學
  • 材料力學
  • 機械工業


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