Improvement of capacitance equivalent thickness, leakage current, and interfacial state density based on crystallized high-k dielectrics/nitrided buffer layer gate stacks

The gate stack composed of tetragonal/cubic ZrO₂ high-K dielectrics and nitrided Al₂O₃ buffer layer was investigated to reduce the capacitance equivalent thickness (CET), leakage current density (Jg), and interfacial state density (Dit). The high-K tetragonal/cubic phase of ZrO₂ was formed by post metallization annealing at a low temperature of 450°C. The Jg was suppressed by the insertion of the Al₂O₃ buffer layer between ZrO ₂ and Si. The remote NH₃ plasma nitridation on the Al ₂O₃ buffer layer further leads to the deactivation of the oxygen vacancies and the well passivation of the Si dangling bonds. Accordingly, a suppressed Jg of 8.12 × 10^-6 A/cm² and Dit of 2.77 × 10¹¹ cm^-2 eV^-1 were achieved in the crystallized ZrO₂/nitrided Al₂O₃ gate stack with a low CET of 1.2 nm. The gate stack was also optically probed through the photoluminescence from Si, revealing that the hydrogen passivation and depassivation effects caused by the remote NH3 plasma treatment are highly correlated with the Dit. The results indicate that the crystallized high-K dielectrics/nitrided buffer layer is a promising gate stack structure to improve the electrical characteristics in the advanced metal-oxide-semiconductor devices.