Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

Ming Huei Lin; Yi Jia Shih; Chien Liu; Yu Chien Chiu; Chia Chi Fan; Guan Lin Liou; Chun Hu Cheng; Chun Yen Chang

doi:10.23919/SNW.2017.8242290

Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

Ming Huei Lin, Yi Jia Shih, Chien Liu, Yu Chien Chiu, Chia Chi Fan, Guan Lin Liou, Chun Hu Cheng^*, Chun Yen Chang

^*此作品的通信作者

機電工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

摘要

This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10⁷. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.

原文	英語
主出版物標題	2017 Silicon Nanoelectronics Workshop, SNW 2017
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	47-48
頁數	2
ISBN（電子）	9784863486478
DOIs	https://doi.org/10.23919/SNW.2017.8242290
出版狀態	已發佈 - 2017 12月 29
事件	22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, 日本持續時間: 2017 6月 4 → 2017 6月 5

出版系列

名字	2017 Silicon Nanoelectronics Workshop, SNW 2017
卷	2017-January

其他

其他	22nd Silicon Nanoelectronics Workshop, SNW 2017
國家/地區	日本
城市	Kyoto
期間	2017/06/04 → 2017/06/05

ASJC Scopus subject areas

電氣與電子工程
電子、光磁材料

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10.23919/SNW.2017.8242290

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引用此

Lin, M. H., Shih, Y. J., Liu, C., Chiu, Y. C., Fan, C. C., Liou, G. L., Cheng, C. H., & Chang, C. Y. (2017). Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. 於 2017 Silicon Nanoelectronics Workshop, SNW 2017 (頁 47-48). 文章 8242290 (2017 Silicon Nanoelectronics Workshop, SNW 2017; 卷 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SNW.2017.8242290

Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. / Lin, Ming Huei; Shih, Yi Jia; Liu, Chien 等.
2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 47-48 8242290 (2017 Silicon Nanoelectronics Workshop, SNW 2017; 卷 2017-January).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Lin, MH, Shih, YJ, Liu, C, Chiu, YC, Fan, CC, Liou, GL, Cheng, CH & Chang, CY 2017, Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. 於 2017 Silicon Nanoelectronics Workshop, SNW 2017., 8242290, 2017 Silicon Nanoelectronics Workshop, SNW 2017, 卷 2017-January, Institute of Electrical and Electronics Engineers Inc., 頁 47-48, 22nd Silicon Nanoelectronics Workshop, SNW 2017, Kyoto, 日本, 2017/06/04. https://doi.org/10.23919/SNW.2017.8242290

Lin MH, Shih YJ, Liu C, Chiu YC, Fan CC, Liou GL 等. Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. 於 2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 47-48. 8242290. (2017 Silicon Nanoelectronics Workshop, SNW 2017). doi: 10.23919/SNW.2017.8242290

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title = "Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect",

abstract = "This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.",

author = "Lin, {Ming Huei} and Shih, {Yi Jia} and Chien Liu and Chiu, {Yu Chien} and Fan, {Chia Chi} and Liou, {Guan Lin} and Cheng, {Chun Hu} and Chang, {Chun Yen}",

note = "Publisher Copyright: {\textcopyright} 2017 JSAP.; 22nd Silicon Nanoelectronics Workshop, SNW 2017 ; Conference date: 04-06-2017 Through 05-06-2017",

year = "2017",

month = dec,

day = "29",

doi = "10.23919/SNW.2017.8242290",

language = "English",

series = "2017 Silicon Nanoelectronics Workshop, SNW 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - GEN

T1 - Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

AU - Lin, Ming Huei

AU - Shih, Yi Jia

AU - Liu, Chien

AU - Chiu, Yu Chien

AU - Fan, Chia Chi

AU - Liou, Guan Lin

AU - Cheng, Chun Hu

AU - Chang, Chun Yen

PY - 2017/12/29

Y1 - 2017/12/29

N2 - This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.

AB - This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.

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U2 - 10.23919/SNW.2017.8242290

DO - 10.23919/SNW.2017.8242290

M3 - Conference contribution

AN - SCOPUS:85051023585

T3 - 2017 Silicon Nanoelectronics Workshop, SNW 2017

SP - 47

EP - 48

BT - 2017 Silicon Nanoelectronics Workshop, SNW 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 22nd Silicon Nanoelectronics Workshop, SNW 2017

Y2 - 4 June 2017 through 5 June 2017

ER -

Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

摘要

出版系列

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ASJC Scopus subject areas

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