Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

Ming Huei Lin, Yi Jia Shih, Chien Liu, Yu Chien Chiu, Chia Chi Fan, Guan Lin Liou, Chun Hu Cheng, Chun Yen Chang

研究成果: 書貢獻/報告類型會議論文篇章

摘要

This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.

原文英語
主出版物標題2017 Silicon Nanoelectronics Workshop, SNW 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面47-48
頁數2
ISBN(電子)9784863486478
DOIs
出版狀態已發佈 - 2017 十二月 29
事件22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, 日本
持續時間: 2017 六月 42017 六月 5

出版系列

名字2017 Silicon Nanoelectronics Workshop, SNW 2017
2017-January

其他

其他22nd Silicon Nanoelectronics Workshop, SNW 2017
國家/地區日本
城市Kyoto
期間2017/06/042017/06/05

ASJC Scopus subject areas

  • 電氣與電子工程
  • 電子、光磁材料

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