Impact of nanoscale polarization relaxation on endurance reliability of one-transistor hybrid memory using combined storage mechanisms

Yu Chien Chiu, Chun Yen Chang, Hsiao Hsuan Hsu, Chun-Hu Cheng, Min-Hung Lee

研究成果: 書貢獻/報告類型會議論文篇章

1 引文 斯高帕斯(Scopus)

摘要

We demonstrate a novel hybrid nonvolatile memory integrated with a charge trapping mechanism and a ferroelectric polarization effect. The hybrid memory features a large threshold voltage window of 2V, fast 20-ns program/erase time, tight switching margin, and long 1012-cycling endurance at 85oC. Such excellent endurance reliability at 85°C can be ascribed to the introduction of charge-trapping node into the design of memory structure that not only weakens temperature-dependent polarization relaxation, but also improves high-temperature endurance reliability.

原文英語
主出版物標題2015 IEEE International Reliability Physics Symposium, IRPS 2015
發行者Institute of Electrical and Electronics Engineers Inc.
頁面MY31-MY35
2015-May
ISBN(電子)9781467373623
DOIs
出版狀態已發佈 - 2015 一月 1
事件IEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, 美国
持續時間: 2015 四月 192015 四月 23

其他

其他IEEE International Reliability Physics Symposium, IRPS 2015
國家/地區美国
城市Monterey
期間2015/04/192015/04/23

ASJC Scopus subject areas

  • 工程 (全部)

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