Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

Ming Dou Ker, Yong Ru Wen, Wen Yi Chen, Chun Yu Lin

研究成果: 書貢獻/報告類型會議貢獻

11 引文 斯高帕斯(Scopus)

摘要

Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the im portant factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.

原文英語
主出版物標題2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
頁面100-103
頁數4
DOIs
出版狀態已發佈 - 2010 十二月 1
事件2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, 臺灣
持續時間: 2010 十一月 182010 十一月 19

出版系列

名字2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

其他

其他2010 International Symposium on Next-Generation Electronics, ISNE 2010
國家臺灣
城市Kaohsiung
期間10/11/1810/11/19

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

指紋 深入研究「Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process」主題。共同形成了獨特的指紋。

  • 引用此

    Ker, M. D., Wen, Y. R., Chen, W. Y., & Lin, C. Y. (2010). Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. 於 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program (頁 100-103). [5669188] (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program). https://doi.org/10.1109/ISNE.2010.5669188