HW/SW Co-design and FPGA Acceleration of a Feature-Based Visual Odometry

In the field of visual odometry (VO) or SLAM, deriving camera poses from image features is the basic issue. Even though feature-based VO or SLAM are more efficient than non-feature-based methods, they are still unfortunately computationally demanding. This paper addresses the concerns of computational efficiency, computational resources and power-consumption problem of a VO algorithm by designing a hardware-software (HW/SW) co-design architecture for the implementation on a field-programmable gate array (FPGA) and a Nios II CPU. Given images from Nios II, features are extracted and matched by SIFT and linear exhausted search (LES) algorithms via hardware. The design of LES module is improved so that the speed is accelerated compared to our previous work. Subsequently, camera poses are estimated using an ICP algorithm, where the derivation of nearest orthogonal matrix is achieved by integrating Denman-Beavers (DB) approach and Taylor approximation method. As such, the required hardware resources are lesser. After hardware computations, the results are then transferred back to Nios II. To show the effectiveness of the proposed approach, experiments using KITTI dataset are conducted. The results show that, taking the advantages of efficient computation of hardware, the computational time is greatly reduced, compared to a full-software implementation. Moreover, usage of hardware resources are also lesser than existing methods.