Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices

J. Y. Wei; S. Maikap; M. H. Lee; C. C. Lee; C. W. Liu

doi:10.1016/j.sse.2005.10.032

Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices

J. Y. Wei, S. Maikap, M. H. Lee, C. C. Lee, C. W. Liu^*

^*此作品的通信作者

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

15 引文斯高帕斯（Scopus）

摘要

Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance-voltage (C-V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect.

原文	英語
頁（從 - 到）	109-113
頁數	5
期刊	Solid-State Electronics
卷	50
發行號	2
DOIs	https://doi.org/10.1016/j.sse.2005.10.032
出版狀態	已發佈 - 2006 2月
對外發佈	是

ASJC Scopus subject areas

電子、光磁材料
凝聚態物理學
電氣與電子工程
材料化學

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10.1016/j.sse.2005.10.032

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title = "Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices",

abstract = "Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance-voltage (C-V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect.",

keywords = "Device simulation, Hole confinement, MOS C-V, Pinning effect, Strain",

author = "Wei, {J. Y.} and S. Maikap and Lee, {M. H.} and Lee, {C. C.} and Liu, {C. W.}",

year = "2006",

month = feb,

doi = "10.1016/j.sse.2005.10.032",

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T1 - Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices

AU - Wei, J. Y.

AU - Maikap, S.

AU - Lee, M. H.

AU - Lee, C. C.

AU - Liu, C. W.

PY - 2006/2

Y1 - 2006/2

N2 - Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance-voltage (C-V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect.

AB - Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance-voltage (C-V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect.

KW - Device simulation

KW - Hole confinement

KW - MOS C-V

KW - Pinning effect

KW - Strain

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JO - Solid-State Electronics

JF - Solid-State Electronics

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Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices

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