Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices

J. Y. Wei, S. Maikap, M. H. Lee, C. C. Lee, C. W. Liu*

*此作品的通信作者

    研究成果: 雜誌貢獻期刊論文同行評審

    14 引文 斯高帕斯(Scopus)

    摘要

    Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance-voltage (C-V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect.

    原文英語
    頁(從 - 到)109-113
    頁數5
    期刊Solid-State Electronics
    50
    發行號2
    DOIs
    出版狀態已發佈 - 2006 二月

    ASJC Scopus subject areas

    • 電子、光磁材料
    • 凝聚態物理學
    • 電氣與電子工程
    • 材料化學

    指紋

    深入研究「Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices」主題。共同形成了獨特的指紋。

    引用此