High throughput and low area cost FPGA-based signature match circuit for network intrusion detection

Wen Jyi Hwang; Chien Min Ou; Ying Nan Shih; Chia Tien dan Lo

doi:10.1080/02533839.2009.9671520

High throughput and low area cost FPGA-based signature match circuit for network intrusion detection

Wen Jyi Hwang, Chien Min Ou^*, Ying Nan Shih, Chia Tien dan Lo

^*此作品的通信作者

資訊工程學系

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

8 引文斯高帕斯（Scopus）

摘要

A novel FPGA-based signature match circuit serving as the core of a hardware-based network intrusion detection system (NIDS) is presented in this paper. The circuit is based on simple shift registers and signature decoders for efficient hardware signature matches. As compared with related work, experimental results show that the proposed work achieves high throughput and uses few hardware resources in the FPGA implementations of NIDS systems.

原文	英語
頁（從 - 到）	397-405
頁數	9
期刊	Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an
卷	32
發行號	3
DOIs	https://doi.org/10.1080/02533839.2009.9671520
出版狀態	已發佈 - 2009

ASJC Scopus subject areas

一般工程

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10.1080/02533839.2009.9671520

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High throughput and low area cost FPGA-based signature match circuit for network intrusion detection. / Hwang, Wen Jyi; Ou, Chien Min; Shih, Ying Nan 等.
於: Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an, 卷 32, 編號 3, 2009, p. 397-405.

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

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High throughput and low area cost FPGA-based signature match circuit for network intrusion detection

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