A novel FPGA-based signature match circuit serving as the core of a hardware-based network intrusion detection system (NIDS) is presented in this paper. The circuit is based on simple shift registers and signature decoders for efficient hardware signature matches. As compared with related work, experimental results show that the proposed work achieves high throughput and uses few hardware resources in the FPGA implementations of NIDS systems.
|頁（從 - 到）||397-405|
|期刊||Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an|
|出版狀態||已發佈 - 2009 一月 1|
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