TY - GEN
T1 - High throughput 32-bit AES implementation in FPGA
AU - Chang, Chi Jeng
AU - Huang, Chi Wu
AU - Chang, Kuo Huang
AU - Chen, Yi G.
AU - Hsieh, Chung Cheng
PY - 2008
Y1 - 2008
N2 - Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature[9].
AB - Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature[9].
UR - http://www.scopus.com/inward/record.url?scp=62949153692&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=62949153692&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2008.4746393
DO - 10.1109/APCCAS.2008.4746393
M3 - Conference contribution
AN - SCOPUS:62949153692
SN - 9781424423422
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 1806
EP - 1809
BT - Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
T2 - APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Y2 - 30 November 2008 through 3 December 2008
ER -