High throughput 32-bit AES implementation in FPGA

Chi Jeng Chang, Chi Wu Huang, Kuo Huang Chang, Yi G. Chen, Chung Cheng Hsieh

研究成果: 書貢獻/報告類型會議貢獻

18 引文 斯高帕斯(Scopus)

摘要

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature[9].

原文英語
主出版物標題Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
頁面1806-1809
頁數4
DOIs
出版狀態已發佈 - 2008 十二月 1
事件APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, 中国
持續時間: 2008 十一月 302008 十二月 3

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

其他

其他APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
國家中国
城市Macao
期間08/11/3008/12/3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • 引用此

    Chang, C. J., Huang, C. W., Chang, K. H., Chen, Y. G., & Hsieh, C. C. (2008). High throughput 32-bit AES implementation in FPGA. 於 Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (頁 1806-1809). [4746393] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2008.4746393