@inproceedings{3b294cdcd3cf4739863556167a21a65f,
title = "High speed negative capacitance ferroelectric memory",
abstract = "This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.",
author = "Chang, {Chun Yen} and Fan, {Chia Chi} and Chien Liu and Chiu, {Yu Chien} and Cheng, {Chun Hu}",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 ; Conference date: 25-10-2017 Through 28-10-2017",
year = "2017",
month = jul,
day = "1",
doi = "10.1109/ASICON.2017.8252397",
language = "English",
series = "Proceedings of International Conference on ASIC",
publisher = "IEEE Computer Society",
pages = "1--5",
editor = "Yajie Qin and Zhiliang Hong and Ting-Ao Tang",
booktitle = "Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017",
}