High speed negative capacitance ferroelectric memory

Chun Yen Chang, Chia Chi Fan, Chien Liu, Yu Chien Chiu, Chun Hu Cheng

研究成果: 書貢獻/報告類型會議論文篇章

摘要

This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 10 12 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.

原文英語
主出版物標題Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
編輯Yajie Qin, Ting-Ao Tang, Zhiliang Hong
發行者IEEE Computer Society
頁面1-5
頁數5
ISBN(電子)9781509066247
DOIs
出版狀態已發佈 - 2018 一月 8
事件12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, 中国
持續時間: 2017 十月 252017 十月 28

出版系列

名字Proceedings of International Conference on ASIC
2017-October
ISSN(列印)2162-7541
ISSN(電子)2162-755X

會議

會議12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
國家/地區中国
城市Guiyang
期間2017/10/252017/10/28

ASJC Scopus subject areas

  • 硬體和架構
  • 電氣與電子工程

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