High speed c-means clustering in reconfigurable hardware

Wen Jyi Hwang*, Chih Chieh Hsu, Hui Ya Li, Sheng Kai Weng, Tsung Yi Yu

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

3 引文 斯高帕斯(Scopus)

摘要

A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on lookup table, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on an FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for c-means design.

原文英語
頁(從 - 到)237-246
頁數10
期刊Microprocessors and Microsystems
34
發行號6
DOIs
出版狀態已發佈 - 2010 十月

ASJC Scopus subject areas

  • 軟體
  • 硬體和架構
  • 電腦網路與通信
  • 人工智慧

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