High-performance poly-Si TFTs using ultrathin HfSiOx gate dielectric for monolithic three-dimensional integrated circuits and system on glass applications

M. H. Lee, S. L. Wu, M. J. Yang, K. J. Chen, G. L. Luo, L. S. Lee, M. J. Kao

研究成果: 雜誌貢獻文章

5 引文 斯高帕斯(Scopus)

摘要

High-performance poly-Si thin-film transistors (TFTs) using an ultrathin high-κ metal gate stack with a subthreshold swing (SS) of 193 mV/dec when operating at room temperature and maximum thermal budget of 700 °C are readily compatible with monolithic 3-D integrated circuits (3D-ICs) and silicon-on-glass (SOG) applications. The SS is reduced to 31 mV/dec, and the on/off current ratio is increased to 108 at 77 K; the result is a significant reduction of leakage current and lower power consumption. Long-channel TFTs have a higher drain current noise spectral density S ID and a smaller exponential frequency factor (γ) due to the influence of numerous grain boundaries on carrier transport, as confirmed by gap state density extraction. These devices may pave the way for high-performance circuit designs and applications, such as monolithic 3D-ICs, SOG, and active-matrix organic LED.

原文英語
文章編號5497075
頁(從 - 到)824-826
頁數3
期刊IEEE Electron Device Letters
31
發行號8
DOIs
出版狀態已發佈 - 2010 八月 1

    指紋

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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