High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

Shih Fen Huang, Chih Yung Lin, Yu Shyang Huang, Thomas Schafbauer, Manfred Eller, Yao Ching Cheng, Shui Ming Cheng, Sandrine Sportouch, Wei Jin, Nivo Rovedo, Andreas Grassmann, Yimin Huang, James Brighten, Chuan H. Liu, Birgit Von Ehrenwall, Norman Chen, Jia Chen, O. Seo Park, Martin Commons, Alan ThomasMing Tsan Lee, Steward Rauch, Larry Clevenger, Erdem Kaltalioglu, Pak Leung, Jenkon Chen, Thomas Schiml, Clement Wann

研究成果: 雜誌貢獻期刊論文同行評審

43 引文 斯高帕斯(Scopus)

摘要

50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.

原文英語
頁(從 - 到)237-240
頁數4
期刊Technical Digest-International Electron Devices Meeting
DOIs
出版狀態已發佈 - 2001
對外發佈

ASJC Scopus subject areas

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程
  • 材料化學

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