50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.
|頁（從 - 到）||237-240|
|期刊||Technical Digest-International Electron Devices Meeting|
|出版狀態||已發佈 - 2001|
ASJC Scopus subject areas