@article{a6eaa9e479e24aeabb64b43c650a0aca,
title = "High performance 50 nm CMOS devices for microprocessor and embedded processor core applications",
abstract = "50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.",
author = "Huang, {Shih Fen} and Lin, {Chih Yung} and Huang, {Yu Shyang} and Thomas Schafbauer and Manfred Eller and Cheng, {Yao Ching} and Cheng, {Shui Ming} and Sandrine Sportouch and Wei Jin and Nivo Rovedo and Andreas Grassmann and Yimin Huang and James Brighten and Liu, {Chuan H.} and {Von Ehrenwall}, Birgit and Norman Chen and Jia Chen and Park, {O. Seo} and Martin Commons and Alan Thomas and Lee, {Ming Tsan} and Steward Rauch and Larry Clevenger and Erdem Kaltalioglu and Pak Leung and Jenkon Chen and Thomas Schiml and Clement Wann",
year = "2001",
doi = "10.1109/IEDM.2001.979474",
language = "English",
pages = "237--240",
journal = "Technical Digest-International Electron Devices Meeting",
issn = "0163-1918",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
}