Hardware implementation of κ-winner-take-all neural network with on-chip learning

Hui Ya Li*, Chien Min Ou, Yi Tsan Hung, Wen Jyi Hwang, Chia Lung Hung

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

5 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel pipelined architecture of the competitive learning (CL) algorithm with κ-winners-take-all activation. The architecture employs a codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. An efficient pipeline architecture is then designed based on the codeword swapping scheme for enhancing the throughput. The CPU time of the NIOS processor executing the CL training with the proposed architecture as an accelerator is measured. Experiment results show that the CPU time is lower than that of other hardware or software implementations running the CL training program with or without the support of custom hardware.

原文英語
主出版物標題Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010
頁面340-345
頁數6
DOIs
出版狀態已發佈 - 2010
事件2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010 - Hong Kong, 中国
持續時間: 2010 十二月 112010 十二月 13

出版系列

名字Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010

其他

其他2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010
國家/地區中国
城市Hong Kong
期間2010/12/112010/12/13

ASJC Scopus subject areas

  • 電腦科學(雜項)

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