Hardware Architecture of Parallel Video Halftoning for Electronic Papers

Wen Chung Kao*, Tsai Ting Yen, Ji Lun Ho

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

摘要

A modified direct binary search (DBS) algorithm which minimizes the flickers on the stationary regions has been proposed for electronic paper (ePaper) in our previous work. Acceptable video quality can be achieved in one iteration, but the high time complexity of DBS algorithm still leads to the difficulty of implementing it on an ePaper system. In general, the ePaper is equipped with a low-power microcontroller. It is infeasible to perform real-time video halftoning on such a hardware platform. This paper presents a novel hardware architecture based on a parallel video halftoning algorithm, for electronic papers. This halftoning engine performs DBS for four pixels in a macro block or in different macro blocks parallelly.

原文英語
主出版物標題2023 International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面699-700
頁數2
ISBN(電子)9798350324174
DOIs
出版狀態已發佈 - 2023
事件2023 International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023 - Pingtung, 臺灣
持續時間: 2023 7月 172023 7月 19

出版系列

名字2023 International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023 - Proceedings

會議

會議2023 International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023
國家/地區臺灣
城市Pingtung
期間2023/07/172023/07/19

ASJC Scopus subject areas

  • 人工智慧
  • 人機介面
  • 資訊系統
  • 資訊系統與管理
  • 電氣與電子工程
  • 媒體技術
  • 儀器

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