摘要
A general interconnection network is proposed, taking into account locality of traffic. The network has log2N - log N maximum intercell delay, but when high locality occurs in the communications, the mean intercell delay decreases to O(1). The problem of how to map processors with a known traffic distribution onto the terminals of the network in order to minimize the mean intercell delay is analyzed and formulated as a quadratic assignment problem. The uses of this network as a partitioner, a permuter, a full switch and a generalized connection network is discussed.
| 原文 | 英語 |
|---|---|
| 頁面 | 297-301 |
| 頁數 | 5 |
| 出版狀態 | 已發佈 - 1989 |
| 對外發佈 | 是 |
| 事件 | International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan 持續時間: 1989 5月 17 → 1989 5月 19 |
其他
| 其他 | International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers |
|---|---|
| 城市 | Taipei, Taiwan |
| 期間 | 1989/05/17 → 1989/05/19 |
ASJC Scopus subject areas
- 一般工程
指紋
深入研究「General interconnection network with the consideration of locality in traffic」主題。共同形成了獨特的指紋。引用此
- APA
- Standard
- Harvard
- Vancouver
- Author
- BIBTEX
- RIS