Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

C. H. Cheng*, K. I. Chou, A. Chin

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

8 引文 斯高帕斯(Scopus)

摘要

We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (Vt) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process.

原文英語
頁(從 - 到)35-38
頁數4
期刊Microelectronic Engineering
109
DOIs
出版狀態已發佈 - 2013

ASJC Scopus subject areas

  • 電子、光磁材料
  • 原子與分子物理與光學
  • 凝聚態物理學
  • 表面、塗料和薄膜
  • 電氣與電子工程

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