FPGA platform for CPU design and applications

Chi Jeng Chang, Chi Wu Huang, Ying Ping Lin, Zen Yi Huang, Teng Kuei Hu

研究成果: 書貢獻/報告類型會議貢獻

2 引文 斯高帕斯(Scopus)

摘要

This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.

原文英語
主出版物標題2005 5th IEEE Conference on Nanotechnology
頁面357-360
頁數4
1
出版狀態已發佈 - 2005
事件2005 5th IEEE Conference on Nanotechnology - Nagoya, 日本
持續時間: 2005 七月 112005 七月 15

其他

其他2005 5th IEEE Conference on Nanotechnology
國家日本
城市Nagoya
期間05/7/1105/7/15

ASJC Scopus subject areas

  • Engineering(all)

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