This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.
|主出版物標題||2005 5th IEEE Conference on Nanotechnology|
|出版狀態||已發佈 - 2005|
|事件||2005 5th IEEE Conference on Nanotechnology - Nagoya, 日本|
持續時間: 2005 七月 11 → 2005 七月 15
|其他||2005 5th IEEE Conference on Nanotechnology|
|期間||05/7/11 → 05/7/15|
ASJC Scopus subject areas