TY - GEN
T1 - FPGA implementation of improved ant colony optimization algorithm for path planning
AU - Hsu, Chen Chien
AU - Wang, Wei Yen
AU - Chien, Yi Hsing
AU - Hou, Ru Yu
AU - Tao, Chin Wang
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/11/14
Y1 - 2016/11/14
N2 - An improved ant colony optimization (ACO) algorithm is proposed in this paper for improving the accuracy of path planning. The main idea of this paper is to avoid local minima by continuously tuning a setting parameter and the establishment of novel mechanisms for updating partial pheromone and opposite pheromone. As a result, the global search of the proposed ACO algorithm can be significantly enhanced in terms of calculating optimal path compared to the conventional ACO algorithm. Simulation results of the proposed approach show better performances in terms of the shortest distance, mean distance, and success rate towards optimal paths. To further reduce the computation time, the proposed ACO algorithm for path planning is realized on a FPGA chip to verify its practicalities. Experimental results indicate that the efficiency of the path planning is significantly improved by the hardware design of embedded applications.
AB - An improved ant colony optimization (ACO) algorithm is proposed in this paper for improving the accuracy of path planning. The main idea of this paper is to avoid local minima by continuously tuning a setting parameter and the establishment of novel mechanisms for updating partial pheromone and opposite pheromone. As a result, the global search of the proposed ACO algorithm can be significantly enhanced in terms of calculating optimal path compared to the conventional ACO algorithm. Simulation results of the proposed approach show better performances in terms of the shortest distance, mean distance, and success rate towards optimal paths. To further reduce the computation time, the proposed ACO algorithm for path planning is realized on a FPGA chip to verify its practicalities. Experimental results indicate that the efficiency of the path planning is significantly improved by the hardware design of embedded applications.
KW - Ant colony optimization (ACO)
KW - Field-programmable gate array (FPGA)
KW - Path planning
KW - Pheromone diffusion mechanism
UR - http://www.scopus.com/inward/record.url?scp=85008259361&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85008259361&partnerID=8YFLogxK
U2 - 10.1109/CEC.2016.7744364
DO - 10.1109/CEC.2016.7744364
M3 - Conference contribution
AN - SCOPUS:85008259361
T3 - 2016 IEEE Congress on Evolutionary Computation, CEC 2016
SP - 4516
EP - 4521
BT - 2016 IEEE Congress on Evolutionary Computation, CEC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE Congress on Evolutionary Computation, CEC 2016
Y2 - 24 July 2016 through 29 July 2016
ER -