First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles

Yu Rui Chen; Yi Chun Liu; Zefu Zhao; Wan Hsuan Hsieh; Jia Yang Lee; Chien Te Tu; Bo Wei Huang; Jer Fu Wang; Shee Jier Chueh; Yifan Xing; Guan Hua Chen; Hung Chun Chou; Dong Soo Woo; M. H. Lee; C. W. Liu

doi:10.23919/VLSITechnologyandCir57934.2023.10185284

First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles

Yu Rui Chen^*, Yi Chun Liu, Zefu Zhao, Wan Hsuan Hsieh, Jia Yang Lee, Chien Te Tu, Bo Wei Huang, Jer Fu Wang, Shee Jier Chueh, Yifan Xing, Guan Hua Chen, Hung Chun Chou, Dong Soo Woo, M. H. Lee, C. W. Liu^*

^*此作品的通信作者

研究成果: 書貢獻/報告類型 › 會議論文篇章

4 引文斯高帕斯（Scopus）

摘要

The large memory window of 1.8V at the low write voltage of 2V is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge0.98Si0.02 FeFETs with the channel phosphorus concentration larger than 1E18cm-3, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of > 1E4 seconds, linearly extrapolated 10 years, and high endurance > 1E11 cycles are also demonstrated. The thermal budget is as low as 400°C. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the 2nm node and beyond.

原文	英語
主出版物標題	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9784863488069
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185284
出版狀態	已發佈 - 2023
對外發佈	是
事件	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, 日本持續時間: 2023 6月 11 → 2023 6月 16

出版系列

名字	Digest of Technical Papers - Symposium on VLSI Technology
卷	2023-June
ISSN（列印）	0743-1562

會議

會議	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
國家/地區	日本
城市	Kyoto
期間	2023/06/11 → 2023/06/16

ASJC Scopus subject areas

電氣與電子工程

存取文件

10.23919/VLSITechnologyandCir57934.2023.10185284

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引用此

Chen, Y. R., Liu, Y. C., Zhao, Z., Hsieh, W. H., Lee, J. Y., Tu, C. T., Huang, B. W., Wang, J. F., Chueh, S. J., Xing, Y., Chen, G. H., Chou, H. C., Woo, D. S., Lee, M. H., & Liu, C. W. (2023). First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. 於 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2023-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185284

First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. / Chen, Yu Rui; Liu, Yi Chun; Zhao, Zefu 等.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2023-June).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Chen, YR, Liu, YC, Zhao, Z, Hsieh, WH, Lee, JY, Tu, CT, Huang, BW, Wang, JF, Chueh, SJ, Xing, Y, Chen, GH, Chou, HC, Woo, DS, Lee, MH & Liu, CW 2023, First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. 於 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Digest of Technical Papers - Symposium on VLSI Technology, 卷 2023-June, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, 日本, 2023/06/11. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185284

Chen YR, Liu YC, Zhao Z, Hsieh WH, Lee JY, Tu CT 等. First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. 於 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir57934.2023.10185284

Chen, Yu Rui ; Liu, Yi Chun ; Zhao, Zefu 等. / First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology).

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title = "First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles",

abstract = "The large memory window of 1.8V at the low write voltage of 2V is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge0.98Si0.02 FeFETs with the channel phosphorus concentration larger than 1E18cm-3, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of > 1E4 seconds, linearly extrapolated 10 years, and high endurance > 1E11 cycles are also demonstrated. The thermal budget is as low as 400°C. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the 2nm node and beyond.",

author = "Chen, {Yu Rui} and Liu, {Yi Chun} and Zefu Zhao and Hsieh, {Wan Hsuan} and Lee, {Jia Yang} and Tu, {Chien Te} and Huang, {Bo Wei} and Wang, {Jer Fu} and Chueh, {Shee Jier} and Yifan Xing and Chen, {Guan Hua} and Chou, {Hung Chun} and Woo, {Dong Soo} and Lee, {M. H.} and Liu, {C. W.}",

note = "Publisher Copyright: {\textcopyright} 2023 JSAP.; 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 ; Conference date: 11-06-2023 Through 16-06-2023",

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doi = "10.23919/VLSITechnologyandCir57934.2023.10185284",

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AU - Liu, Yi Chun

AU - Zhao, Zefu

AU - Hsieh, Wan Hsuan

AU - Lee, Jia Yang

AU - Tu, Chien Te

AU - Huang, Bo Wei

AU - Wang, Jer Fu

AU - Chueh, Shee Jier

AU - Xing, Yifan

AU - Chen, Guan Hua

AU - Chou, Hung Chun

AU - Woo, Dong Soo

AU - Lee, M. H.

AU - Liu, C. W.

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AB - The large memory window of 1.8V at the low write voltage of 2V is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge0.98Si0.02 FeFETs with the channel phosphorus concentration larger than 1E18cm-3, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of > 1E4 seconds, linearly extrapolated 10 years, and high endurance > 1E11 cycles are also demonstrated. The thermal budget is as low as 400°C. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the 2nm node and beyond.

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T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

PB - Institute of Electrical and Electronics Engineers Inc.

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First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles

摘要

出版系列

會議

ASJC Scopus subject areas

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