First demonstration of flash RRAM on pure CMOS logic 14nm FinFET platform featuring excellent immunity to sneak-path and MLC capability

E. R. Hsieh, Y. C. Kuo, C. H. Cheng, J. L. Kuo, M. R. Jiang, J. L. Lin, H. W. Cheng, Steve S. Chung, C. H. Liu, T. P. Chen, Y. H. Yeah, T. J. Chen, Osbert Cheng

研究成果: 書貢獻/報告類型會議論文篇章

3 引文 斯高帕斯(Scopus)

摘要

For the first time, the ion-vacancy-based bipolar RRAM has been demonstrated on HKMG stack of FEOL logic 14nm FinFET. A unit cell with two identical FinFETs, one serves as a control transistor and the other one is the storage with resistance switching. It is performed by the edge tunneling and with bipolar switching. More importantly, the sneak path issue in an AND-type array based on this FinFET unit cell has been thoroughly investigated. To solve sneak path issue, a new active-fin-isolation (AFI) of FinFET in an AND-type array was proposed. This new AFI effectively increases the S/N margin of 103 and significantly reduces the standby power of 30% and active power of 99%, compared to original AND-type array. This work provides a promising candidate for the embedded FLASH memory on FinFET platform featuring fully-CMOS compatible integration and low cost solution in the more-than-Moore era.

原文英語
主出版物標題2017 Symposium on VLSI Technology, VLSI Technology 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面T72-T73
ISBN(電子)9784863486058
DOIs
出版狀態已發佈 - 2017 7月 31
對外發佈
事件37th Symposium on VLSI Technology, VLSI Technology 2017 - Kyoto, 日本
持續時間: 2017 6月 52017 6月 8

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
ISSN(列印)0743-1562

會議

會議37th Symposium on VLSI Technology, VLSI Technology 2017
國家/地區日本
城市Kyoto
期間2017/06/052017/06/08

ASJC Scopus subject areas

  • 電氣與電子工程

指紋

深入研究「First demonstration of flash RRAM on pure CMOS logic 14nm FinFET platform featuring excellent immunity to sneak-path and MLC capability」主題。共同形成了獨特的指紋。

引用此