TY - GEN
T1 - Ferroelectric HfZrO FETs for Emerging Technologies
AU - Lee, Min Hung
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/8
Y1 - 2020/8
N2 - The prospect of ferroelectric Hf-based oxide by ALD (Atomic Layer Deposition) with bistable states nature feature of hysteresis loops satisfies the demands of the storage signal purpose for memory and the voltage amplification concept for negative capacitance (NC). Si doping in HfO2 to form a ferroelectric material was discovered by Qimonda AG in 2010; recently, ferroelectric Hf-based oxide materials have been used in many applications, such as memory, negative capacitance, passive component, and solar cells. For the Al (Artificial lntelligence) and loT (lnternet of Things) era, the requirement of scaling down supply voltage VDD and power consumption for low power devices is the pursued goals for CMOS and memory applications. The ferroelectric gate stack is integrated into FETs with NC effect for subthreshold swing (SS) improvement. The feasible concept of coupling the polarization Hf-based oxide is practicable to following current CMOS architectures.
AB - The prospect of ferroelectric Hf-based oxide by ALD (Atomic Layer Deposition) with bistable states nature feature of hysteresis loops satisfies the demands of the storage signal purpose for memory and the voltage amplification concept for negative capacitance (NC). Si doping in HfO2 to form a ferroelectric material was discovered by Qimonda AG in 2010; recently, ferroelectric Hf-based oxide materials have been used in many applications, such as memory, negative capacitance, passive component, and solar cells. For the Al (Artificial lntelligence) and loT (lnternet of Things) era, the requirement of scaling down supply voltage VDD and power consumption for low power devices is the pursued goals for CMOS and memory applications. The ferroelectric gate stack is integrated into FETs with NC effect for subthreshold swing (SS) improvement. The feasible concept of coupling the polarization Hf-based oxide is practicable to following current CMOS architectures.
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U2 - 10.1109/VLSI-TSA48913.2020.9203683
DO - 10.1109/VLSI-TSA48913.2020.9203683
M3 - Conference contribution
AN - SCOPUS:85093698613
T3 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
SP - 148
BT - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Y2 - 10 August 2020 through 13 August 2020
ER -