摘要
A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.
原文 | 英語 |
---|---|
頁(從 - 到) | 595-600 |
頁數 | 6 |
期刊 | International Journal of Electronics |
卷 | 75 |
發行號 | 4 |
DOIs | |
出版狀態 | 已發佈 - 1993 10月 |
對外發佈 | 是 |
ASJC Scopus subject areas
- 電氣與電子工程