Fast neural decoders for some cyclic codes

Yuen Hsien Tseng; Ja Ling Wu

doi:10.1080/00207219308907135

Fast neural decoders for some cyclic codes

Yuen Hsien Tseng, Ja Ling Wu

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.

原文	英語
頁（從 - 到）	595-600
頁數	6
期刊	International Journal of Electronics
卷	75
發行號	4
DOIs	https://doi.org/10.1080/00207219308907135
出版狀態	已發佈 - 1993 十月
對外發佈	是

ASJC Scopus subject areas

電氣與電子工程

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10.1080/00207219308907135

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title = "Fast neural decoders for some cyclic codes",

abstract = "A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.",

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Fast neural decoders for some cyclic codes

摘要

ASJC Scopus subject areas

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其它文件與鏈接

指紋

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