Fast neural decoders for some cyclic codes

Yuen-Hsien Tseng, Ja Ling Wu

研究成果: 雜誌貢獻文章

1 引文 斯高帕斯(Scopus)

摘要

A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.

原文英語
頁(從 - 到)595-600
頁數6
期刊International Journal of Electronics
75
發行號4
DOIs
出版狀態已發佈 - 1993 一月 1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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