Fabrication and electron transport in vertical silicon-silicon nitride-silicon multilayer nano-pillars

Shu Fen Hu, Hsien Hsun Yang, Heng Tien Lin, Chin Lung Sung, Yue Min Wan

研究成果: 書貢獻/報告類型會議貢獻

摘要

We have designed vertical single-electron transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. A part of surrounding gate arranges source, gate and drain vertically. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. The part surrounding gate transistor has a large effective channel width because the pillar silicon island is so small (< 10 nm) that can be used as a current channel region. Coulomb gap, Coulomb staircases and periodic current oscillation are observed at 300 K. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.

原文英語
主出版物標題2005 5th IEEE Conference on Nanotechnology
頁面745-748
頁數4
DOIs
出版狀態已發佈 - 2005 十二月 1
事件2005 5th IEEE Conference on Nanotechnology - Nagoya, 日本
持續時間: 2005 七月 112005 七月 15

出版系列

名字2005 5th IEEE Conference on Nanotechnology
2

其他

其他2005 5th IEEE Conference on Nanotechnology
國家日本
城市Nagoya
期間05/7/1105/7/15

    指紋

ASJC Scopus subject areas

  • Engineering(all)

引用此

Hu, S. F., Yang, H. H., Lin, H. T., Sung, C. L., & Wan, Y. M. (2005). Fabrication and electron transport in vertical silicon-silicon nitride-silicon multilayer nano-pillars. 於 2005 5th IEEE Conference on Nanotechnology (頁 745-748). [1500825] (2005 5th IEEE Conference on Nanotechnology; 卷 2). https://doi.org/10.1109/NANO.2005.1500825