ESD protection for the tolerant I/O circuits using PESD implantation

Howard T.H. Tang, S. S. Chen, Scott Liu, M. T. Lee, C. H. Liu, M. C. Wang, M. C. Jeng

研究成果: 雜誌貢獻文章

16 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call "PESD" implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μ process, this method provides a significant improvement in the cascode ESD performance.

原文英語
頁(從 - 到)293-300
頁數8
期刊Journal of Electrostatics
54
發行號3-4
DOIs
出版狀態已發佈 - 2002 三月 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Biotechnology
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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    Tang, H. T. H., Chen, S. S., Liu, S., Lee, M. T., Liu, C. H., Wang, M. C., & Jeng, M. C. (2002). ESD protection for the tolerant I/O circuits using PESD implantation. Journal of Electrostatics, 54(3-4), 293-300. https://doi.org/10.1016/S0304-3886(01)00157-7