TY - GEN
T1 - ESD protection design for high-speed circuits in nanoscale CMOS process
AU - Lin, Chun Yu
AU - Chang, Rong Kun
N1 - Funding Information:
This work was supported in part by Ministry of Science and Technology (MOST), Taiwan, under Contract of MOST 105-2622-E-003-001-CC2, and in part by Amazing Microelectronic Corp., Taiwan.
Publisher Copyright:
© 2016 IEEE.
PY - 2017/1/23
Y1 - 2017/1/23
N2 - To protect the high-speed integrated circuits from electrostatic discharge (ESD) damages, the ESD protection design of inductor-assisted silicon-controlled rectifier (LASCR) is investigated in this work. Compared with the conventional ESD protection design of dual-diode, the LASCR has better high-speed performances and higher ESD robustness. Therefore, the LASCR is very suitable for high-speed applications.
AB - To protect the high-speed integrated circuits from electrostatic discharge (ESD) damages, the ESD protection design of inductor-assisted silicon-controlled rectifier (LASCR) is investigated in this work. Compared with the conventional ESD protection design of dual-diode, the LASCR has better high-speed performances and higher ESD robustness. Therefore, the LASCR is very suitable for high-speed applications.
KW - CMOS
KW - electrostatic discharge (ESD) protection
KW - high-speed circuits
UR - http://www.scopus.com/inward/record.url?scp=85013769785&partnerID=8YFLogxK
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U2 - 10.1109/ISICIR.2016.7829726
DO - 10.1109/ISICIR.2016.7829726
M3 - Conference contribution
AN - SCOPUS:85013769785
T3 - 2016 International Symposium on Integrated Circuits, ISIC 2016
BT - 2016 International Symposium on Integrated Circuits, ISIC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 International Symposium on Integrated Circuits, ISIC 2016
Y2 - 12 December 2016 through 14 December 2016
ER -