TY - GEN
T1 - ESD protection design for high-speed applications in CMOS technology
AU - Chen, Jie Ting
AU - Lin, Chun Yu
AU - Chang, Rong Kun
AU - Ker, Ming Dou
AU - Tzeng, Tzu Chien
AU - Lin, Tzu Chiang
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/2
Y1 - 2016/7/2
N2 - To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded siliconcontrolled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.
AB - To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded siliconcontrolled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.
UR - http://www.scopus.com/inward/record.url?scp=85015877405&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85015877405&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2016.7870016
DO - 10.1109/MWSCAS.2016.7870016
M3 - Conference contribution
AN - SCOPUS:85015877405
T3 - Midwest Symposium on Circuits and Systems
BT - 2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016
Y2 - 16 October 2016 through 19 October 2016
ER -