ESD protection design for high-speed applications in CMOS technology

Jie Ting Chen, Chun Yu Lin, Rong Kun Chang, Ming Dou Ker, Tzu Chien Tzeng, Tzu Chiang Lin

研究成果: 書貢獻/報告類型會議論文篇章

3 引文 斯高帕斯(Scopus)

摘要

To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded siliconcontrolled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.

原文英語
主出版物標題2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509009169
DOIs
出版狀態已發佈 - 2016 七月 2
事件59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 - Abu Dhabi, 阿拉伯聯合酋長國
持續時間: 2016 十月 162016 十月 19

出版系列

名字Midwest Symposium on Circuits and Systems
0
ISSN(列印)1548-3746

其他

其他59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016
國家/地區阿拉伯聯合酋長國
城市Abu Dhabi
期間2016/10/162016/10/19

ASJC Scopus subject areas

  • 電子、光磁材料
  • 電氣與電子工程

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