TY - GEN
T1 - ESD Protection Design for Fan-Out Panel-Level Packaging
AU - Lin, Chun Yu
AU - Hsieh, Chia You
AU - Dai, Zih Jyun
AU - Lai, Yu Hsuan
N1 - Publisher Copyright:
© 2022 EOS/ESD Association, Inc.
PY - 2022
Y1 - 2022
N2 - With a new concept of hetero-integration by combining display and functional redistribution layer (RDL) technologies, the fan-out panel-level package (FOPLP) technology with ESD protection design is studied in this work. The proposed ESD protection circuits in RDL are realized by low temperature poly silicon thin film transistor, and the circuits are used to protect a CMOS inverter. The ESD protection circuits for FOPLP applications are verified in this work.
AB - With a new concept of hetero-integration by combining display and functional redistribution layer (RDL) technologies, the fan-out panel-level package (FOPLP) technology with ESD protection design is studied in this work. The proposed ESD protection circuits in RDL are realized by low temperature poly silicon thin film transistor, and the circuits are used to protect a CMOS inverter. The ESD protection circuits for FOPLP applications are verified in this work.
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M3 - Conference contribution
AN - SCOPUS:85144609254
T3 - International EOS/ESD Symposium on Design and System, IEDS 2022
BT - International EOS/ESD Symposium on Design and System, IEDS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd Annual International EOS/ESD Symposium on Design and System, IEDS 2022
Y2 - 9 November 2022 through 11 November 2022
ER -