TY - GEN
T1 - ESD protection consideration in nanoscale CMOS technology
AU - Ker, Ming Dou
AU - Lin, Chun Yu
PY - 2011
Y1 - 2011
N2 - The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.
AB - The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.
KW - CMOS
KW - electrostatic discharge (ESD)
KW - on-chip ESD protection
UR - http://www.scopus.com/inward/record.url?scp=84858969202&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84858969202&partnerID=8YFLogxK
U2 - 10.1109/NANO.2011.6144345
DO - 10.1109/NANO.2011.6144345
M3 - Conference contribution
AN - SCOPUS:84858969202
SN - 9781457715143
T3 - Proceedings of the IEEE Conference on Nanotechnology
SP - 720
EP - 723
BT - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011
T2 - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011
Y2 - 15 August 2011 through 19 August 2011
ER -