ESD protection consideration in nanoscale CMOS technology

Ming Dou Ker*, Chun Yu Lin

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

7 引文 斯高帕斯(Scopus)

摘要

The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.

原文英語
主出版物標題2011 11th IEEE International Conference on Nanotechnology, NANO 2011
頁面720-723
頁數4
DOIs
出版狀態已發佈 - 2011 十二月 1
事件2011 11th IEEE International Conference on Nanotechnology, NANO 2011 - Portland, OR, 美国
持續時間: 2011 八月 152011 八月 19

出版系列

名字Proceedings of the IEEE Conference on Nanotechnology
ISSN(列印)1944-9399
ISSN(電子)1944-9380

其他

其他2011 11th IEEE International Conference on Nanotechnology, NANO 2011
國家/地區美国
城市Portland, OR
期間2011/08/152011/08/19

ASJC Scopus subject areas

  • 生物工程
  • 電氣與電子工程
  • 材料化學
  • 凝聚態物理學

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