TY - GEN
T1 - Embedded PUF on 14nm HKMG FinFET Platform
T2 - 39th Symposium on VLSI Technology, VLSI Technology 2019
AU - Hsieh, E. R.
AU - Wang, H. W.
AU - Liu, C. H.
AU - Chung, Steve S.
AU - Chen, T. P.
AU - Huang, S. A.
AU - Chen, T. J.
AU - Cheng, Osbert
N1 - Publisher Copyright:
© 2019 The Japan Society of Applied Physics.
PY - 2019/6
Y1 - 2019/6
N2 - In this work, a novel concept of 2-bit-per-cell (2B/C) is introduced to realize high-density OTP PUF from a new scheme of dielectric breakdown. This PUF shows 105x of large window, good immunity to high-temperature disturbance, and excellent retention under 150°C baking, which are particularly for automotive applications. In terms of security, this PUF exhibits near ideal normal distribution of hamming distance and narrow distribution of hamming weight. The bit error rates are low, 0.78% at 25°C and 1.95% at 150°C, benchmarked on a 256-bit array. Finally, the security test of this PUF against the hackers' attack from the machine learning process has been proved to have high security. Overall, the proposed 2B/C OTP PUF demonstrated great potential for IoT security in 5G era.
AB - In this work, a novel concept of 2-bit-per-cell (2B/C) is introduced to realize high-density OTP PUF from a new scheme of dielectric breakdown. This PUF shows 105x of large window, good immunity to high-temperature disturbance, and excellent retention under 150°C baking, which are particularly for automotive applications. In terms of security, this PUF exhibits near ideal normal distribution of hamming distance and narrow distribution of hamming weight. The bit error rates are low, 0.78% at 25°C and 1.95% at 150°C, benchmarked on a 256-bit array. Finally, the security test of this PUF against the hackers' attack from the machine learning process has been proved to have high security. Overall, the proposed 2B/C OTP PUF demonstrated great potential for IoT security in 5G era.
UR - http://www.scopus.com/inward/record.url?scp=85070317748&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85070317748&partnerID=8YFLogxK
U2 - 10.23919/VLSIT.2019.8776515
DO - 10.23919/VLSIT.2019.8776515
M3 - Conference contribution
AN - SCOPUS:85070317748
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - T118-T119
BT - 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 June 2019 through 14 June 2019
ER -