Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era

E. R. Hsieh, H. W. Wang, C. H. Liu, Steve S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, Osbert Cheng

研究成果: 書貢獻/報告類型會議貢獻

摘要

In this work, a novel concept of 2-bit-per-cell (2B/C) is introduced to realize high-density OTP PUF from a new scheme of dielectric breakdown. This PUF shows 105x of large window, good immunity to high-temperature disturbance, and excellent retention under 150°C baking, which are particularly for automotive applications. In terms of security, this PUF exhibits near ideal normal distribution of hamming distance and narrow distribution of hamming weight. The bit error rates are low, 0.78% at 25°C and 1.95% at 150°C, benchmarked on a 256-bit array. Finally, the security test of this PUF against the hackers' attack from the machine learning process has been proved to have high security. Overall, the proposed 2B/C OTP PUF demonstrated great potential for IoT security in 5G era.

原文英語
主出版物標題2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面T118-T119
ISBN(電子)9784863487178
DOIs
出版狀態已發佈 - 2019 六月
事件39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, 日本
持續時間: 2019 六月 92019 六月 14

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2019-June
ISSN(列印)0743-1562

會議

會議39th Symposium on VLSI Technology, VLSI Technology 2019
國家日本
城市Kyoto
期間19/6/919/6/14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Hsieh, E. R., Wang, H. W., Liu, C. H., Chung, S. S., Chen, T. P., Huang, S. A., Chen, T. J., & Cheng, O. (2019). Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era. 於 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (頁 T118-T119). [8776515] (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776515