Embedded a low area 32-bit AES for image encryption/decryption application

Kuo Huang Chang; Yi Cheng Chen; Chung Cheng Hsieh; Chi Wu Huang; Chi Jeng Chang

doi:10.1109/ISCAS.2009.5118159

Embedded a low area 32-bit AES for image encryption/decryption application

Kuo Huang Chang^*, Yi Cheng Chen, Chung Cheng Hsieh, Chi Wu Huang, Chi Jeng Chang

^*此作品的通信作者

工業教育學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

14 引文斯高帕斯（Scopus）

摘要

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

原文	英語
主出版物標題	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
頁面	1922-1925
頁數	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5118159
出版狀態	已發佈 - 2009
事件	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, 臺灣持續時間: 2009 5月 24 → 2009 5月 27

出版系列

名字	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN（列印）	0271-4310

其他

其他	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
國家/地區	臺灣
城市	Taipei
期間	2009/05/24 → 2009/05/27

ASJC Scopus subject areas

電氣與電子工程

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10.1109/ISCAS.2009.5118159

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Chang, K. H., Chen, Y. C., Hsieh, C. C., Huang, C. W., & Chang, C. J. (2009). Embedded a low area 32-bit AES for image encryption/decryption application. 於 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 (頁 1922-1925). 文章 5118159 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2009.5118159

Chang, KH, Chen, YC, Hsieh, CC, Huang, CW & Chang, CJ 2009, Embedded a low area 32-bit AES for image encryption/decryption application. 於 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5118159, Proceedings - IEEE International Symposium on Circuits and Systems, 頁 1922-1925, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, 臺灣, 2009/05/24. https://doi.org/10.1109/ISCAS.2009.5118159

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abstract = "Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.",

author = "Chang, {Kuo Huang} and Chen, {Yi Cheng} and Hsieh, {Chung Cheng} and Huang, {Chi Wu} and Chang, {Chi Jeng}",

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AB - Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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Embedded a low area 32-bit AES for image encryption/decryption application

摘要

出版系列

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ASJC Scopus subject areas

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其它文件與鏈接

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