Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.
|主出版物標題||2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009|
|出版狀態||已發佈 - 2009|
|事件||2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, 臺灣|
持續時間: 2009 五月 24 → 2009 五月 27
|其他||2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009|
|期間||2009/05/24 → 2009/05/27|
ASJC Scopus subject areas