Embedded a low area 32-bit AES for image encryption/decryption application

Kuo Huang Chang, Yi Cheng Chen, Chung Cheng Hsieh, Chi Wu Huang, Chi Jeng Chang

研究成果: 書貢獻/報告類型會議貢獻

8 引文 斯高帕斯(Scopus)

摘要

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

原文英語
主出版物標題2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
頁面1922-1925
頁數4
DOIs
出版狀態已發佈 - 2009
事件2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, 臺灣
持續時間: 2009 五月 242009 五月 27

其他

其他2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
國家臺灣
城市Taipei
期間09/5/2409/5/27

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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