Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm

Wen-Jyi Hwang, Hao Chen

研究成果: 書貢獻/報告類型會議論文篇章

1 引文 斯高帕斯(Scopus)

摘要

A novel hardware architecture for fast spike sorting is presented in this paper. The architecture is able to perform feature extraction based on the Generalized Hebbian Algorithm (GHA). The employment of GHA allows efficient computation of principal components for subsequent clustering and classification operations. The hardware implementations of GHA features high throughput and low area costs. The proposed architecture is implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip(SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining low hardware resource utilization and high speed computation.

原文英語
主出版物標題ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning
頁面71-76
頁數6
出版狀態已發佈 - 2013 十一月 11
事件21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013 - Bruges, 比利时
持續時間: 2013 四月 242013 四月 26

出版系列

名字ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning

其他

其他21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013
國家/地區比利时
城市Bruges
期間2013/04/242013/04/26

ASJC Scopus subject areas

  • 人工智慧
  • 資訊系統

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