Efficient pipelined architecture for competitive learning

Hui Ya Li, Chia Lung Hung, Wen-Jyi Hwang*, Yi Tsan Hung

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel pipelined architecture for competitive learning (CL). The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for reducing the computation time. In the architecture, a novel codeword swapping scheme is adopted so that neuron competitions for different training vectors can be operated concurrently. The neuron updating process is based on a hardware divider with simple table lookup operations. The divider performs finite precision calculations for area cost reduction at the expense of slight degradation in training performance. The CPU time of the NIOS processor executing the CL training with the proposed architecture as an accelerator is measured. Experimental results show that the NIOS processor with the proposed architecture as an accelerator can achieve up to a speedup of 254 over its software counterpart running on a general purpose processor Pentium IV without hardware support.

原文英語
頁(從 - 到)236-244
頁數9
期刊Journal of Parallel and Distributed Computing
71
發行號2
DOIs
出版狀態已發佈 - 2011 二月 1

ASJC Scopus subject areas

  • 軟體
  • 理論電腦科學
  • 硬體和架構
  • 電腦網路與通信
  • 人工智慧

指紋

深入研究「Efficient pipelined architecture for competitive learning」主題。共同形成了獨特的指紋。

引用此