This paper presents a novel hardware architecture for memetic vector quantizer (VQ) design. The architecture uses steady-state genetic algorithm (GA) for global search, and C-Means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state CA operations. It also uses a pipeline architecture for the hardware implementation of C-Means algorithm. The proposed architecture is embedded in a softcore CPU, and implemented on a field programmable logic array (FPGA) device for physical performance measurement. Experimental results show that the proposed architecture is an effective method for VQ optimization attaining both high performance and low computational time.
|頁（從 - 到）||905-914|
|期刊||Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an|
|出版狀態||已發佈 - 2009 一月 1|
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