Efficient logic circuit for network intrusion detection

Huang Chun Roan; Chien Min Ou; Wen Jyi Hwang; Chia Tien Dan Lo

doi:10.1007/11802167_78

Efficient logic circuit for network intrusion detection

Huang Chun Roan, Chien Min Ou, Wen Jyi Hwang^*, Chia Tien Dan Lo

^*此作品的通信作者

資訊工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

5 引文斯高帕斯（Scopus）

摘要

A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection.

原文	英語
主出版物標題	Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings
發行者	Springer Verlag
頁面	776-784
頁數	9
ISBN（列印）	3540366792, 9783540366799
DOIs	https://doi.org/10.1007/11802167_78
出版狀態	已發佈 - 2006
事件	International Conference on Embedded and Ubiquitous Computing, EUC 2006 - Seoul, 大韓民國持續時間: 2006 8月 1 → 2006 8月 4

出版系列

名字	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
卷	4096 LNCS
ISSN（列印）	0302-9743
ISSN（電子）	1611-3349

其他

其他	International Conference on Embedded and Ubiquitous Computing, EUC 2006
國家/地區	大韓民國
城市	Seoul
期間	2006/08/01 → 2006/08/04

ASJC Scopus subject areas

理論電腦科學
一般電腦科學

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10.1007/11802167_78

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引用此

Roan, H. C., Ou, C. M., Hwang, W. J., & Lo, C. T. D. (2006). Efficient logic circuit for network intrusion detection. 於 Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings (頁 776-784). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 卷 4096 LNCS). Springer Verlag. https://doi.org/10.1007/11802167_78

Efficient logic circuit for network intrusion detection. / Roan, Huang Chun; Ou, Chien Min; Hwang, Wen Jyi 等.
Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings. Springer Verlag, 2006. p. 776-784 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 卷 4096 LNCS).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Roan, HC, Ou, CM, Hwang, WJ & Lo, CTD 2006, Efficient logic circuit for network intrusion detection. 於 Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 卷 4096 LNCS, Springer Verlag, 頁 776-784, International Conference on Embedded and Ubiquitous Computing, EUC 2006, Seoul, 大韓民國, 2006/08/01. https://doi.org/10.1007/11802167_78

Roan HC, Ou CM, Hwang WJ, Lo CTD. Efficient logic circuit for network intrusion detection. 於 Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings. Springer Verlag. 2006. p. 776-784. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/11802167_78

Roan, Huang Chun ; Ou, Chien Min ; Hwang, Wen Jyi 等. / Efficient logic circuit for network intrusion detection. Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings. Springer Verlag, 2006. 頁 776-784 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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AB - A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection.

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Efficient logic circuit for network intrusion detection

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